structure-model via statement

The structure-model statement defines delay and loss models used by signal integrity constraints for signals through vias. Each statement defines a model for a new pair of layers. Layers can be specified as a side (e.g. Top or Bottom) or a LayerIndex (e.g. LayerIndex(0, Top)). Models are assumed to be symmetric so the order of the given layers is arbitrary. It is an error to specify multiple models for the same pair of layers. It is recommended to not specify models with the same start and end layer. They will currently be ignored by the constraint solver (since path does not travel through the via) but this behavior may change in a future version of JITX. The models are given in terms of the same PinModel object used by components.

The simplest way to use structure-model is to specify the exact layers and models, e.g.:

public pcb-via example-via :
  structure-model(Top, Bottom) = PinModel(tol(5.e-15), tol(0.05))
  ; ...other via parameters

Not all pairs of layers need to be specified. If you know that, e.g. all usages of a via will go between the top and bottom of the board, then only that model needs to be provided.

Via models can also be specified in a loop, e.g.:

public pcb-via multi-model-via :
  ; Define a PinModel that is linear in the number of layers
  ; For maximum accuracy it would likely be better to simulate each specific pair of layers
  defn n-layer-model (n-layers:Int):
    PinModel(
      tol(2.e-12 * to-double(n-layers)),
      tol(0.05 * to-double(n-layers)))

  val total-layers = 4
  for i in 0 to total-layers do:
    for j in (i + 1) to total-layers do:
      structure-model(LayerIndex(i,Top), LayerIndex(j,Top)) = n-layer-model(j - i)

  ; ...other via parameters